Bay Area Circuits’ standard tolerances are listed below.  Designing a PCB with these tolerances in mind will help ensure the finished product meets expectations.  Tighter tolerances may be available on request; please contact us for more information if a standard tolerance does not meet needed specifications.



Tolerance: Hole size + 0.020”
Design Tip: Ensure that holes for both vias and components do not come within 0.010” of copper from a different net.



Tolerance: +/- 0.005”, unless a scored array is required (see below)
Design Tip: Keep outer layer copper at least 0.005” away from the board edge and inner layer copper at least 0.010” away from the board edge.  Leave more space on the inner layers because inner layers can shift and because the pre-preg needs to adhere to the layers above and below.  Some exceptions are necessary, such as gold fingers, which usually meet the board edge.



Locational Tolerance: +/- 0.003”
Depth tolerance: +/- 0.005”
Design Tip: Use these tolerances and some trigonometry to determine how close your copper can come to a scored edge.  Remember that the center of the score line is the edge of your board.



Tolerance: +/- 0.003”
Design Tip: Pads for plated holes must be at least 0.010” larger than the plated hole to ensure an IPC 6012 annular ring.



Tolerance: +/- 0.003” for plated holes less than 0.247” in diameter, +/- 0.002” for nonplated holes less than 0.250” in diameter, +/- 0.005” for larger holes



Tolerance: +/- 0.005”



Tolerance: +/- 0.005” nonplated, +/- 0.010” plated



Tolerance: +/- 10% or +/- 0.005”, whichever is greater



Tolerance: +/- 20%



Tolerance: +/- 20%



Tolerance: +/- 0.003”
Design Tip: Soldermask clearances should be 0.003” larger than their pads (this distance is sometimes called a “soldermask swell”).  With a standard minimum soldermask dam of 0.004”, components whose pads are within 0.010” of each other may require special processing.

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